Signal r2_data : std_logic_vector(1 downto 0) Signal r1_data : std_logic_vector(1 downto 0)
Signal r0_data : std_logic_vector(1 downto 0) O_data : out std_logic_vector(1 downto 0)) I_data : in std_logic_vector(1 downto 0) The three descriptions are totally equivalent.Ī plain description of the shift registers in Figure 1 is reported in the VHDL code below. Figure 1 shift register architecture exampleĪs stated before, there are at least three different ways to describe such hardware structure in VHDL.
